Logic analyzer update:
I’ve ported two projects, a continuous sampling LA that works with sig-rok, and a hardware capture LA that goes fast and works with a custom client. The firmware is posted somewhere around here, and the ports are in the repo on various branches.
I planned to port the second one to the Bus Pirate and adapt it to use SUMP protocol with sig-rok. Well, a few days ago I noticed it is GPL licensed, and we’re MIT licensed, so it’s kind of poor situation without the author’s express permission. I’ve talked to him on github before so maybe that’s possible. But, after digging a bit I’m not sure its the right implementation for BP because it focuses on multiple chained devices for massive parallel analysis. Still an AMAZING project.
I found this project, which is a DMA-based capture LA that already works with SUMP. I cannibalized the SUMP interface because it already "speaks rp2040’ and saved me a day porting the old ugly state machine from Bus Pirate 3. However, the speed is low and the triggers are in software. It makes up for it with a focus on RLE, which is cool. Unfortunately I absolutely cannot get it to work consistently, I believe there are DMA and interrupt conflicts messing with the state machine and debugging has been slow.
So, I’m going to refresh myself on RP2040 DMA by studying Paul’s DSO code again, and bringing up the little arbitrary wave generator board I made a while ago. Then I’ll dig into making a from scratch logic analyzer.
Logic analyzer thoughts
- RP2040 DMA supports a ring buffer mode, but when I studied it before it lacked some important piece to easily make a logic analyzer. I need to remember why.
- Using PIO for some kind of trigger mode and sample down-count and halt. GusmanB’s project has a lot of inspiration for this, but he also uses a 4 section ping pong buffer instead of a ring buffer.
ETA: When I was poking around PIO counters, I came upon this frequency counter. Is this something that might interest anyone?