The next binary mode thing I’m tackling is the logic analyzer. I’m going to port the sigrok-pico project because it seems the best stress tested and they have support accepted by sigrok:
The speed is really solid, but we won’t be able to have the full 220K buffer they use because we need a lot of RAM for the other goodies in the Bus Pirate firmware.
I’m going to do a bare port first to fit it to the hardware. It will take some work to integrate it into the Bus Pirate firmware because it is so heavily optimized for speed.
A supporting version of sigrok for windows is available here:
This is a test firmware for pico_sdk_sigrok. The logic analyzer blocks all the other Bus Pirate functions in this test, it will be integrated soon.
This is a continuous sample logic analyzer, and all triggering is done in the sig-rok client. It uses run length encoding to compress the samples and achieve higher speeds with the limited USB CDC bandwidth.
On my setup, speeds up to 2.5MHz are sustainable on a slow bus.
While small (<100K) samples can run up to 120MSPS, since there are no hardware triggers it just takes records immediately and dumps back to sig-rok.
The pico_sdk_sigrok project requires a patched version of sig-rok. The project has a patch accepted to sig-rok for testing. Linux folks cam probably compile it without much trouble, for Windows a compiled version is available
UARTs/configuration
Two UARTS will connect in this firmware. The lower number is the debug terminal, the higher number is used by sigrok. It’s probably a good idea to open a terminal and view the debug info, otherwise the USB buffers may fill up and the Bus Pirate will freeze.
Remember to power the buffer
Put some kind of voltage on the VOUT/VREF pin to power the Bus Pirate IO buffer or the logic analyzer won’t record anything. This allows compatibility with a wide range of logic levels in the 1.8-5.0volt range. In the future it would be nice to use the Bus Pirate power supply and allow the voltage to be set from the sig-rok client.
This is a test firmware for El Dr. Gusman Logic Analyzer . The logic analyzer blocks all the other Bus Pirate functions in this test, it will be integrated soon.
This is a sample and dump logic analyzer with hardware triggers in the PIO. It waits for the trigger and then records as many pre/post trigger samples specified, up to the buffer maximum (138K). Speeds up to 100MSPS are possible.
This type of logic analyzer is easy to port to the SUMP protocol, then it will work with sigrok out of the box, as well as a number of other software UIs.
UARTs/configuration
Two UARTs will connect in this firmware. The lower number does nothing, the higher number is used by the logic analyzer.
Remember to power the buffer
Put some kind of voltage on the VOUT/VREF pin to power the Bus Pirate IO buffer or the logic analyzer won’t record anything. This allows compatibility with a wide range of logic levels in the 1.8-5.0volt range. In the future it would be nice to use the Bus Pirate power supply and allow the voltage to be set from the client.
Danger! Overclocked!
The firmware overclocks the RP2040 to 200MHz. Evidently most (all?) boards will work at this speed. If you have a problem please let me know.
Only simple edge triggers
Using the complex triggers uses up two IO pins that have to be tied together. For now it supports simple triggers only.
