Logic Analyzer Mode

Development
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I’ve ordered my BP 5 (yay!) and I’m eager to explore it but I want to know if there’s some kind of logic analyzer mode

I’d like to know:

  • is there a way to just see the signals in real time on screen
  • store them (where?)
  • work with saleae logic and/or sigrok/pulseview (I imagine a binary protocol implementation is going to be fairly easy but not optimized)
  • if all the 8 channels are used, what kind of sampling frequency should I expect (in real life, I know that abs max is 125MHz)?
  • after sampling them can we try to decode them?

thanks

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Some people have worked on rp2040 LA’s. There’s μLA and sigrok itself had a pico driver merged into the main code. More info is Here. The second project even has a getting started page. Looking at both docs, they say 100 MHz - 120 MHz capture speed, And you can use pulseview to decode signals

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Hey dzervas,

Thank you so much for checking out the Bus Pirate.

The LCD doesn’t show logic output yet, but paul and i talked about adding a graphics library to support more stuff like that. I’m not very good with displays, but maybe it will get some attention from the community as well.

I have ported two logic analyzers to the hardware so far. they are both dedicated builds (require firmware swap) at the moment.

One logic analyzer is a continuous sampling type, it does infinite samples and can do 3-12msps depending on how fast the data is changing. It samples, RLE encodes/compresses the samples, and shoves them through the serial port as fast as possible. This mode is compatible with sigrok, and all triggers are handled in sigrok on the raw data stream. This is similar to how the Saleae logic and similar work.

The second logic analyzer uses the PIO to do all kinds of fancy hardware triggers. This one samples at 125MSPS (max) into a 128K ring buffer. When a trigger is detected up to 128K samples are collected and dumped back to the PC. The project this code comes from, Dr. Gusman B, has a custom logic analyzer client. I was pretty close to getting this implemented in the main bus pirate firmware before we hit the manufacturing crunch. The version implemented in the main Bus Pirate firmware will use the SUMP protocol supported by sigrok and others.

Decoding is generally handled on the software client. I’m excited to play with sniffers though, the PIO makes it very easy to sniff and decode SPI, I2C, 1-Wire, etc, which we can log to the internal storage or show in the display.

3 Likes
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Thanks for you awesome work @ian!
Woah even 1MSps is more than I’d need (given that BP isn’t the tool too debug a PCI lane :joy: )

I’m sure the community will tightly hug the project and we’ll see/write amazing stuff! Can’t wait to get my hands on it :slight_smile:

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thanks for the links!

I was hoping for built-in support (would make the process MUCH easier than swapping firmware) but I’ll just have to wait/contribute :slight_smile:

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its coming! ive been on hardware and production for the past month, but I’m back to firmware today. The LA integration was the last thing i worked, it just needs a bit more work. i hope to have a look today, but theres some other priority cleanup i have to do first.

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Thank you, Ian. We appreciate it - but don’t overwork yourself. We can wait.