Hello all,
Thank you for your patience, I debugged this today. There should be an auto build with a fix for this issue on Bus Pirate 5 hardware.
The fix
.pio_version 0 // only requires PIO version 0
.program logicanalyzer_no_trigger
Explicitly specified the pio version in logicanalyzer.pio. This was not a fix.
#define PIO_RGB_LED_PIO pio0
#define PIO_RGB_LED_SM 1
#define PIO_LOGIC_ANALYZER_PIO pio0
#define PIO_LOGIC_ANALYZER_SM 0
Swapped the logic analyzer state machine from pio0.1 to pio0.0. This fixes the freezing while running pulseview.
Why?
It’s never nice not to know why a bug fix works. I suspect there are some deeper bugs in the PICO SDK 2.0 with regards to the PIO that may or may not play a role. I have found and reported what appears to be a nasty bug in the new functions to claim and release state machines, which is why the PIO and SM is currently hard coded.
//setup interrupts
pio_interrupt_clear(pio_config.pio, 0);
pio_set_irq0_source_enabled(pio_config.pio, pis_interrupt0, true);
irq_set_exclusive_handler(PIO0_IRQ_0 + (PIO_NUM(pio_config.pio)*2), logic_analyser_done);
irq_set_enabled(PIO0_IRQ_0 + (PIO_NUM(pio_config.pio)*2), true);
//this will probably need a mutex
void logic_analyser_done(void) {
// turn off stuff!
pio_interrupt_clear(pio_config.pio, 0);
irq_set_enabled(PIO0_IRQ_0+ (PIO_NUM(pio_config.pio)*2), false);
// irq_set_enabled(pio_get_dreq(pio_config.pio, pio_config.sm, false), false);
irq_remove_handler(PIO0_IRQ_0+ (PIO_NUM(pio_config.pio)*2), logic_analyser_done);
pio_sm_set_enabled(pio_config.pio, pio_config.sm, false);
With dynamic allocation of PIO/SM we needed to also set the interrupt handlers dynamically. At the time I did not find a Pico-native way to do this, and hacked together the PIO0_IRQ_0 + (PIO_NUM(pio_config.pio)*2)
based on a look at the register addresses.
It is 101% possible this is the source of the bug. Maybe someone with sharp eyes will see what I’ve done wrong.
For the time being, the current fix works. When they release an updated SDK we can take another stab at dynamic PIO allocation.