Si5351 plank ◦◦◦◦◦◦◦◦◦◦

General
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Continuing the discussion from Breakout board demos:

Note that skyworksinc has a full software package to configure this chip … so it’s definitely a complex beast.

This thread is to start discussion on what use(s) this might have, if creating a plank (and some software) around this part.

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There is a cut off. Two can be over a certain frequency and the rest (depending on package) cannot. That was my take away. If people want an interface Ill build one.

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  1. For hackerspace scenarios, it seems the B variant that adjusts frequency based on an input voltage might be non-useful (too much precision required)? [but please correct me] Thus, I’ll focus on A and C…

  2. What sorts of hackerspace scenarios would benefit from having up to eight(+) unique frequencies being output?

  3. The default configuration is set in OTP memory. Thus, my thoughts on this being infinitely-reconfigurable when attached to the buspirate, and then running stand-alone, are quashed! This plank will only be usable with active configuration sent over I2C each powerup.

  4. Am I reading this correctly (see page 3)?

    • The A variant routes the OSC input to both PLL A and PLL B.
    • Both A and C allow an external clock input via XA.
    • The C variant allows a second external clock via CLKIN.
    • The C variant has a crossbar switch for PLL A and PLL B.
    • In other words, the C variant can be configured to do anything the A variant can do, and  has the additional options for using a second external clock?
    • Thus, C is only needed when needing to synchronize clock outputs with two distinct  external clock domains?

  5. How much work is it to convert the official configuration files into a stream of commands to configure the chip? Figure 10 makes it look like it’s fairly simple?

(+) Only two unique frequencies above 112.5 MHz  can be simultaneously output. For eight frequencies, do they each have to be < 112.5MHz, or can two of the eight be >112.5MHz, with six slows frequencies?

Other notes

Pin Usage Notes
XA Crystal or external clock synchronized outputs
XB Crystal
CLKIN External clock C variant only, second synchronized domain
OEB Output enable pull-up (disable) by default?
SSEN Spread Spectrum pull-up (enable) by default?
INTR Interrupt for problems Tie to an error LED?
VDD 3V3 power supply
VDDO1 Outputs 1, 2 Allow external power via jumper?
VDD02 Outputs 3, 4 Allow external power via jumper?
VDDO3 Outputs 5, 6 Allow external power via jumper?
VDD04 Outputs 7, 8 Allow external power via jumper?

If such a plank were created, maybe provide some default configurations that were generated by their software, and allow users to load the text-based output from their software?

e.g., Don’t re-invent the configuration software, and provide some samples for known use cases?

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I don’t have any need for this type of chip. Just was interesting to understand some of the limitations imposed, and try to guess at the underlying “why”. :slight_smile:

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