Would anyone be open / willing to design a simple Schematic in KiCad for me?
I have a really hard time finding the appropriate parts:
voltage regulator (fixed, 3V3)
IDC connector for JLink
3x machine-pin connector for BusPirate
The goal is that I can take the schematic (with parts thus defined), and I can create a small PCB with the necessary orientation, distances, mounting holes, etc.
It’s OK to leave the machined pins unpopulated if using a through-hole footprint… I can get the machined pins from Amazon if needed.
The goal is to be able to just order fully populated PCBs from DirtyPCBs or another low-cost protoype board shop, and then be able to use my JLink (and RTTViewer, and …).
I really only need the schematic (and thus parts and footprints found and assigned)… I am happy to create the PCB. Hopefully this is a tiny project for those familiar with the process, as it would save me many hours of frustration to get this assistance.
That schematic looks great! Best if it’s something I can send to DirtyPCBs where they can just populate (at least) the LDO, resistors, and LED (with SMD parts). I don’t know what I don’t know, but I’ve sent fully-passive boards out before.
One change I’ll make is to put the LED on the 3V3 side. Both ensures the LDO is working, and because I don’t like bright light.
Can you share the schematic? Is it setup with all SMD parts, or are any pass-through pin?
Sure I’ll move the LED. I have not assigned component footprints, it’s whatever I copy pasted out of the bus pirate schematic. I assume it will be 0603 or 0805. We will have 20 hand assembled at the dodgy assembler, I assume, but that’s up to @jin.
The weird thing is we can design and fab 20 of these for half what the official adapter costs.
ensure that when the target is unpowered no voltage is driven into SWCLK and SWDIO
Usually VTref is designed to be directly taken from the voltage supply of the target, so that VTref is 0V when the target is unpowered. When you now hook up a voltage regulator that is permanently powered by the Jlink to VTref, the second function isn’t ensured in hardware anymore. You rely on the Jlink firmware handling this case correctly.
Do not connect a BusPirate or other target, just the Jlink alone
Connect 5V_supply with a jumper wire to VTref, so that the Jlink thinks the target uses 5V as IO-voltage
connect a high pulldown to ground, for example 100k, on SWDIO and SWCLK. This could be for example on a breadboard or fly-wires.
Hook a oscilloscope probe to SWCLK, single shot, trigger on rising edge
Use the Jlink software to try to connect to a SWD target
Do you see a voltage pulse on SWCLK?
Repeat the same with SWDIO
There should be no voltage pulses on SWCLK or SWDIO. If this is the case then the firmware of the Jlink works properly and won’t damage an unpowered bus pirate or other target.
If there is a voltage pulse, then an unpowered Bus Pirate or other target could be damaged and I suggest to add some pullup-sensing protection circuitry.
I’ll try this sometime this week… I had a good burst of time with RTT, will update with results.
Can you help me reduce my ignorance by correcting my errors?
If I instruct the JLink to connect to a SWD target, which only has SWCLK, SWDIO, and GND connection, wouldn’t the JLink necessarily need to pulse at least the SWCLK line?
Put another way, how would a debug probe differentiate between an unpowered chip being connected vs. nothing being connected?
Moreover, if the voltage is 3V3 (matching the buspirate required level), and the pins are connected to the buspirate debug header, is it really dangerous to probe for the chip when it’s not powered by toggling SWCLK and/or SWDIO?
As a final note, I don’t see anything like this on Segger’s own pictures of their official units, nor anything in their block diagram. Still, will try to investigate using your steps.
I checked both SWO and SWCLK … neither one triggered the oscilliscope. To verify the trigger, I touched VSupply directly, and the oscilliscope’s trigger … triggered. Does this mean the JLink does some magic before toggling the lines?
I was using the wrong pins. Yes, the JLink toggles both the SWCLK and SWDIO lines.
The target is supposed to have weak pullups on SWDIO and SWCLK. So the probe firmware can check for a logic high level before activating it’s outputs.
The pins are specified IOVDD + 0.5 V abs. max. When the BP is unpowered, IOVDD is 0, so the maximum allowed voltage would be 0.5V. So a pulse with 3.3V will violate that.
Ok, so their firmware doesn’t play it safe and does not protect the target in this case.
An adapter board could use something like a simple 74LVC2G17 to sense the logic level on SWCLK: First gate to sense SWCLK, probably a 1M pulldown on SWCLK. Output of the first gate through a resistor to a small cap. R/C designed so that the low-part of like a 10kHz SWCLK signal discharges the cap half way. The resistor is bridged by a diode so that a high level immediately charges the cap. The input to the second gate is taken off the cap and the output goes to the enable of the voltage regulator that powers VTref.
Downside of this protection circuitry is that it only protects against powering up SWD on an unpowered target. It does not protect against disconnecting the power from a target while SWD is still active. Implementing a protection against the latter is vastly more complex.
But if you use just a breakout-cable and not an adapter board you have to be careful to just enable the voltage of the Jlink when you are sure the target is powered via USB. I know from my own experience of heated debugging sessions that it is easy to forget this one time and then the target in danger. So I prefer to have some kind of protection built in.
Segger has a vast lineup of current and past probe hardware variants and generations. It could very well be that not all of them support setting an arbitrary VTref-voltage.
When this affects only older or more exotic probe hardware it could also explain the price: only very few people actually need this adapter.
Wow … the things I learn … confirmed from RP2040 datasheet, section 5.3.3.1, “Absolute Maximum Ratings”. I’m just surprised that, without power, applying such a small voltage is out-of-spec. I would have expected the pins to safely tolerate 3V3, even when unpowered. Thanks for this learning!
Are the pins really that sensitive, or is Vmax defined with an unwritten presumption that IOVDD is being used at (nominal / approximately) 3V3 levels?
Usually IO-pins have protection diodes to GND and Vcc. So when the IC is unpowered, all voltage higher than the forward voltage goes through these diodes. When there is no sufficient external resistance in series, the current will blow out these diodes.
So a very short pulse might be ok, but if the current is running for seconds the diodes can blow.
I remember blowing a few IO pins this way on some STM32 with UART-RX being driven from the outside while they were unpowered. It depends on how the IO structures are implemented in detail how susceptible a specific IC is. Hard to say just from the datasheet. Just that it is more of an issue with modern ICs with smaller process nodes than it was with older ones - for example the old Atmegas usually didn’t have an issue with this.
@Ian, Turns out it’s still reallly nice to use a proper JLink. If you’ve assembled any of these boards already, can you let me know so I can order a few?
I’d like four, actually. I want to tape them to my BusPirates directly, so I don’t have to ever remove them … just change which one is connected to the JLink. I am happy to pay for them!
