No, I haven’t had a chance to investigate the SPI ADC further yet. We’ll get the quote tomorrow though.
I have a few scattered thoughts on the SPI DAC. Such as, using the 4 MUX address control bits as a second SPI bus dedicated to the ADC. It would avoid a lot of the complexity of sharing one bus with LCD and NAND while maintaining similar speeds as the internal ADC.
For the BP7 REV0A:
- Will swap the 10uF for the switch circuit with a 4.7uf and the lower value resistor
- 68R ohms series resistor on the pins?
- This morning we managed to find a supply of the 2Gbit NAND, so the prototypes will be populated with that
- Board will go out tomorrow