Feel free to review and push any changes. I won’t make further changes today.
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I’m currently having a look.
Does using a 200R resistor (R103) for the ADC_AVDD work well for the RP2350? Or would it be better to reduce the resistor because ADC_AVDD sags sufficiently?
I don’t have a RP2350 (for example a Rev 6) at hand to measure.
With the 10µF the filtering will be improved, so we could maybe reduce the resistor. 100R is already on the BOM and would probably be enough for filtering.
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It was done according to the RPi engineers’ request. I had to submit for a design review before they gave me reels of chips and that was part of the requirements and prerelease PDF slides, etc.
I don’t know about the sag, but the rp2350 ADC is much improved from 2040. The current measurement doesn’t bounce around anymore, so I consider it a winner.
We can adjust and test though 
Yeah, filtering there is a requirement and totally makes sense.
But I’m wondering if 200R or 100R is the better value when paired with the 10µF cap.
But the size is the same, so I can play with it once I have a BP7 Rev0 in hand.
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It was not just a requirement for filtering, but the exact values and for some components the manufacturer and part number.
My understanding is they had not fully qualified the chip and they gave us some guard rails to prevent a rough launch. (Keeps other thoughts to myself).
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What is the 200R resistor (R208) in series with the gate of the display backlight FET for?
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Good practice? I know it’s not strictly needed but I usually use one if a uC is driving it after reading a bunch of app notes years ago. I’m not militant about that.
I don’t think it is necessary in this case.
Something like this makes sense when you have a high-current driving FET and you want to prevent a big inrush-current or similar.
But this FET is driving like 60mA and the gate charge of a FET of this kind is tiny and will never overdrive the output of the MCU.
I suggest to remove it.
My contribution for BOM cost reduction today 
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We can buy chips freely in the market now so we are under no obligation to follow any of the old rules
Go wild. We can make 5pcs, blow them up, and turn 7R1 in a month or so. And then blow that one up. No rush to stop blowing things up.
I’ll keep my piezo grill lighter ready for sure!
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I had the flu that’s ransacking the Netherlands that morning and your grill lighter antics were the highlight of my day.
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If you want to test the 100R on AVDD then we should get that in the R0 BOM as well.
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And maybe that gate resistor to 0ohms?
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We can also leave it as it is for now and once I have a Rev0 at hand take out my multimeter and measure if it is an issue at all. Also changing this resistor on my prototype is easy, we are talking 0402 here, not 01005 or something.
This has worked for Rev6 and was requested by RPi, so it can’t be that bad.
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Yes. Then we should see if this has any negative effects.
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Would your thoughts change if one of the most common failures of assembly was the LCD soldering and often involved LED shorts to ground?
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No, this wouldn’t matter. The LEDs would already short to ground at the connector. No current would flow through the FET.
If this is an issue, I suggest to move the 33R current limiting resistor we currently have between LED-K and the FET to between VUSB and LED-A.
This way it would limit the current flowing into the LCD connector if it were shorted to ground.
It shouldn’t matter if you put a LED current limiting resistor on the anode or cathode.
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I created a new pull request: Small improvements by electroniceel · Pull Request #2 · DangerousPrototypes/BusPirate5-hardware · GitHub
The change with the LCD backlight resistor is included as I suggested.
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Merged. That is a nice list of updates and BOM refinement.
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I can’t find the comment to reply - but I want to emphasize that I very much desire and plan to include the full VOUT protection in the next design increment. It is a tough fit in the current layout, but I’m confident we’ll get there incrementally.
Any way to make this happen is on the table. Maybe the SPI ADC update nets us enough space. If not, two layer is definitely something to pursue if only for the experience. The option I’m not a fan of is a castellated daughter board - castellated boards are filthy expensive to make (at least in that past, at our volumes).
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